Physical Design Intern

8 Months ago • All levels

Job Summary

Job Description

Positions are open for full-time and co-op/internship in the areas of CPU and SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as Place & Route, timing, floorplan, clocking, electrical analysis, and power. Responsibilities include owning block level design from RTL to GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. Collaborate with Micro-architects for feasibility studies and PPA tradeoffs. Develop physical design methodologies and customize recipes for optimization. Work with a multi-functional engineering team to implement and validate physical design using signoff flows like Timing, Power, EM/IR, and PDV.

Must have:

RTL-to-GDSII block level design
Synthesis, floor-planning, place & route
Timing closure and signoff
Feasibility studies and PPA tradeoffs
Physical design methodologies
Signoff flows (Timing, Power, EM/IR, PDV)
CAD tools for synthesis, P&R, analysis, verification
Logic & physical design principles
Low-power & higher-performance designs
Scripting (Unix, Perl, Python, TCL)
Device physics knowledge
Verilog and SystemVerilog knowledge
Problem solving skills
Good communication and organization skills
Self-motivated
Teamwork and ability to meet deadlines

6 skills required

6 skills required for this role

Add these skills to join the top 1% applicants for this job

cad-computer-aided-design

unity

unix

level-design

python

perl

Job Details

Responsibilities

Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.

Requirements

Knowledge using synthesis, place & route, analysis and verification CAD tools.
Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL.
Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.